module regPC (
    /*AUTOARG*/
   // Outputs
   pc,
   // Inputs
   clock, reset, newpc
   );

input           clock;
input           reset;
input  [31:0]   newpc;
output [31:0]   pc;

/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [31:0]              pc;
// End of automatics
always @(posedge clock, posedge reset) begin
    if(reset) begin
        pc <= 32'h0000_0000;
    end else begin
        pc <= newpc;
    end
end


endmodule

